IBM says it can fit nearly 100 billion transistors on a chip - why the milestone matters

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TSMC, Intel, and Samsung have all been pushing to produce low‑single‑nanometer chips in the next two years, while planning to produce sub-nanometer chips sometime by decade's end. That race may be over, however, even before it began. IBM unveiled what it says is the world's first sub-1-nanometer chip technology based on a new 3D NanoStack transistor architecture at the 0.7 nm — or 7 angstrom — node.

The research device, introduced ahead of VLSI 2026 , is designed to pack nearly 100 billion transistors on a fingernail‑size die, roughly doubling the density of IBM's earlier 2-nm test chip, first shown in 2021. Today, the smallest, most powerful chips top out at about 80 billion transistors.

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What's so important about teeny-tiny chips? They're valuable because they let you pack more transistors into a given area while using less power, which translates into higher performance, lower energy use, and lower cost per unit of compute. In case you've been living under a rock, AI demands low-power, cheap chips. There's a huge market for these chips.

At the heart of the announcement is NanoStack. This is a three‑dimensional, nanosheet‑based transistor design that scales vertically, or along the z‑axis, by stacking and staggering CMOS devices. Unlike today's nanosheet architectures, which IBM also pioneered and which are being adopted by leading foundries at 3 nm and 2 nm, NanoStack bonds two nanosheet transistors into a single vertical structure, with each tier optimized independently and contacted from opposite sides.

Each transistor in the demonstrated structure uses three sub-5 nm‑thick nanosheets, about "15 silicon atoms" across, separated by roughly 9 nm spacers. Two such devices are then bonded vertically using an ultra‑thin dielectric process IBM describes as a key innovation. Because the top and bottom devices can use different channel materials, dielectrics, and metals, IBM argues NanoStack is less a single trick and more a transistor platform that can be extended through multiple generations: 7 angstrom (Å), 5 Å, 3 Å, and potentially down to 1 Å in its internal roadmap.

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An angstrom, by the by, is one ten-billionth of a meter. In terms of chips, an angstrom is a tenth of a nanometer.

"This is the world's first sub‑1 nanometer chip technology with a new transistor architecture," said Jay Gambetta, Director of IBM Research and IBM Fellow, during a press briefing. "We're not just making smaller transistors, we're reinventing how chips are built to deliver dramatically more power and energy efficiency."