IBM unveils chip technology to extend Moore's Law

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IBM has built a new prototype chip with around 100 billion transistors on an area the size of a fingernail, which is twice the density of the company's previous state-of-the-art technology announced in 2021. The design could pave the way for faster and more energy efficient computers for years to come. For more than half a century, chipmakers have been able to make ever more powerful computers by following the key principle of Moore's Law: Cram more transistors onto the chip.

To do this, they shrank transistors—the tiny switches that perform computations—to incrementally smaller sizes. But in the last 15 years, transistors have gotten close to the point where quantum mechanics starts to interfere with their function: just a few dozen nanometers in size. They can't get smaller.

So to fit more transistors on a chip, engineers across the industry are eyeing a pivot to an approach familiar to urban planners: build up. On Thursday, IBM announced it has created a chip that uses this strategy. The new architecture, known as a nanostack, vertically stacks transistors in two layers on a silicon chip.

"It's not just an incremental step," Jay Gambetta, the director of IBM Research, said during a press conference on Tuesday. "It's a meaningful leap forward." Within a decade, Gambetta expects, chips with nanostacking will be widely used in data centers, where their improved efficiency could help the facilities better manage their energy consumption. "Absolutely, it's transformational," says Dan Hutcheson, vice chair of TechInsights, a technology analysis company.

"This puts another 10, 15 years on the roadmap." Compared with IBM's previous state-of-the-art architecture, the company reports, chips built with this new approach can do as much as 50% more work in the same amount of time and be up to 70% more energy efficient. The architecture offers a general way of laying out transistors, and IBM will partner with semiconductor manufacturers to make the actual chips. It anticipates that chip designers will deploy the design in many different types of chips, including GPUs and CPUs.

"I expect to have many conversations with designers about how they can use this technology," Huiming Bu, IBM's vice president of global semiconductor R&D, said in the press conference announcing the new design. Engineers created IBM's new chip layer by layer, like a cake. They start by fabricating transistors on one layer of silicon.

Then they place a silicon layer on top of these devices, and they fabricate another layer of transistors directly on top of that. Finally, they create the electrical connections between the two layers of transistors. This kind of vertical stack, which combines two types of transistors, is known as a complementary field-effect transistor, or CFET, explains Qing Cao, a professor of materials science and engineering at the University of Illinois at Urbana-Champaign, who was not involved with the work.